Sciweavers

143 search results - page 15 / 29
» Multiprocessor Support for Event-Driven Programs
Sort
View
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
13 years 9 days ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas
PPOPP
1990
ACM
14 years 19 days ago
Multi-Model Parallel Programming in Psyche
Many different parallel programming models, including lightweight processes that communicate with shared memory and heavyweight processes that communicate with messages, have been...
Michael L. Scott, Thomas J. LeBlanc, Brian D. Mars...
ICS
1999
Tsinghua U.
14 years 26 days ago
Improving the performance of speculatively parallel applications on the Hydra CMP
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
Kunle Olukotun, Lance Hammond, Mark Willey
MICRO
2009
IEEE
168views Hardware» more  MICRO 2009»
14 years 3 months ago
Ordering decoupled metadata accesses in multiprocessors
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
Hari Kannan
HPCA
2011
IEEE
13 years 9 days ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...