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ASPLOS
2008
ACM
13 years 9 months ago
Accurate branch prediction for short threads
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to e...
Bumyong Choi, Leo Porter, Dean M. Tullsen
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 11 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
PC
1998
202views Management» more  PC 1998»
13 years 7 months ago
BSPlib: The BSP programming library
BSPlib is a small communications library for bulk synchronous parallel (BSP) programming which consists of only 20 basic operations. This paper presents the full de nition of BSPl...
Jonathan M. D. Hill, Bill McColl, Dan C. Stefanesc...
ASPLOS
2011
ACM
12 years 11 months ago
RCDC: a relaxed consistency deterministic computer
Providing deterministic execution significantly simplifies the debugging, testing, replication, and deployment of multithreaded programs. Recent work has developed deterministic...
Joseph Devietti, Jacob Nelson, Tom Bergan, Luis Ce...
ISCA
2008
IEEE
130views Hardware» more  ISCA 2008»
14 years 1 months ago
Corona: System Implications of Emerging Nanophotonic Technology
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
Dana Vantrease, Robert Schreiber, Matteo Monchiero...