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VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 8 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
14 years 8 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
HPCA
2008
IEEE
14 years 8 months ago
Branch-mispredict level parallelism (BLP) for control independence
A microprocessor's performance is fundamentally limited by the rate at which it can resolve branch mispredictions. Control independence (CI) architectures look for useful con...
Kshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin...
ICALP
2009
Springer
14 years 8 months ago
Fast FAST
We present a randomized subexponential time, polynomial space parameterized algorithm for the k-Weighted Feedback Arc Set in Tournaments (k-FAST) problem. We also show that our alg...
Noga Alon, Daniel Lokshtanov, Saket Saurabh
ICALP
2009
Springer
14 years 8 months ago
When Are Timed Automata Determinizable?
In this paper, we propose an abstract procedure which, given a timed automaton, produces a language-equivalent deterministic infinite timed tree. We prove that under a certain boun...
Christel Baier, Nathalie Bertrand, Patricia Bouyer...