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GLVLSI
1996
IEEE
125views VLSI» more  GLVLSI 1996»
13 years 11 months ago
Performance-Driven Interconnect Global Routing
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
Dongsheng Wang, Ernest S. Kuh
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
13 years 11 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
ISAAC
1992
Springer
132views Algorithms» more  ISAAC 1992»
13 years 11 months ago
Generalized Assignment Problems
In the multilevel generalized assignment problem (MGAP) agents can perform tasks at more than one efficiency level. Important manufacturing problems, such as lot sizing, can be ea...
Silvano Martello, Paolo Toth
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...