In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
In the multilevel generalized assignment problem (MGAP) agents can perform tasks at more than one efficiency level. Important manufacturing problems, such as lot sizing, can be ea...
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...