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MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
14 years 2 months ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...
DATE
2010
IEEE
159views Hardware» more  DATE 2010»
14 years 25 days ago
A rapid prototyping system for error-resilient multi-processor systems-on-chip
—Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only...
Matthias May, Norbert Wehn, Abdelmajid Bouajila, J...
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
14 years 1 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
JAVA
2001
Springer
14 years 5 days ago
A scalable, robust network for parallel computing
CX, a network-based computational exchange, is presented. The system’s design integrates variations of ideas from other researchers, such as work stealing, non-blocking tasks, e...
Peter R. Cappello, Dimitros Mourloukos
SP
2002
IEEE
147views Security Privacy» more  SP 2002»
13 years 7 months ago
CX: A scalable, robust network for parallel computing
CX, a network-based computational exchange, is presented. The system's design integrates variations of ideas from other researchers, such as work stealing, non-blocking tasks...
Peter R. Cappello, Dimitros Mourloukos