983 search results - page 152 / 197 » Negative-Weight Cycle Algorithms |
MICRO
2008
IEEE
14 years 4 months ago
2008
IEEE
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
ARITH
2007
IEEE
14 years 4 months ago
2007
IEEE
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
DATE
2007
IEEE
14 years 4 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
ICRA
2007
IEEE
14 years 4 months ago
2007
IEEE
Abstract— We describe a fast method to relocalise a monocular visual SLAM (Simultaneous Localisation and Mapping) system after tracking failure. The monocular SLAM system stores ...
INFOCOM
2007
IEEE
14 years 4 months ago
2007
IEEE
Abstract—In this paper we address the problem of energyefficient event detection in wireless sensor networks (WSNs). Duty cycling is a fundamental approach to conserving energy i...