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VLSISP
2008
147views more  VLSISP 2008»
13 years 5 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
AINA
2008
IEEE
14 years 1 months ago
WS-BPEL Process Compiler for Resource-Constrained Embedded Systems
Process management and workflow systems play an important role in the composition of services in business as well as automation environments. Processes are designed using tools a...
Hendrik Bohn, Andreas Bobek, Frank Golatowski
IEEEPACT
2009
IEEE
14 years 2 months ago
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
Basilio B. Fraguela, Yevgen Voronenko, Markus P&uu...
EUROSYS
2007
ACM
14 years 4 months ago
Removing the memory limitations of sensor networks with flash-based virtual memory
Virtual memory has been successfully used in different domains to extend the amount of memory available to applications. We have adapted this mechanism to sensor networks, where,...
Andreas Lachenmann, Pedro José Marró...
ASPDAC
2011
ACM
217views Hardware» more  ASPDAC 2011»
12 years 11 months ago
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core syst
This paper studies realization and performance comparison of the sequential and weak consistency models in the network-on-chip (NoC) based distributed shared memory (DSM) multi-cor...
Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jants...