Sciweavers

7587 search results - page 1474 / 1518
» Network Analysis and Visualisation
Sort
View
INFOCOM
2007
IEEE
14 years 2 months ago
Iterative Scheduling Algorithms
— The input-queued switch architecture is widely used in Internet routers due to its ability to run at very high line speeds. A central problem in designing an input-queued switc...
Mohsen Bayati, Balaji Prabhakar, Devavrat Shah, Ma...
IPPS
2007
IEEE
14 years 2 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
IPPS
2007
IEEE
14 years 2 months ago
Max-Min Fair Bandwidth Allocation Algorithms for Packet Switches
With the rapid development of broadband applications, the capability of networks to provide quality of service (QoS) has become an important issue. Fair scheduling algorithms are ...
Deng Pan, Yuanyuan Yang
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
14 years 2 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
ADBIS
2007
Springer
124views Database» more  ADBIS 2007»
14 years 1 months ago
Fast and Efficient Log File Compression
Contemporary information systems are replete with log files, created in multiple places (e.g., network servers, database management systems, user monitoring applications, system se...
Przemyslaw Skibinski, Jakub Swacha
« Prev « First page 1474 / 1518 Last » Next »