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VLSID
2006
IEEE
136views VLSI» more  VLSID 2006»
14 years 9 months ago
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal
Serial links in network on chip provide advantages in terms of reduced wiring area, reduced switch complexity and power. However, serial links offer lower bandwidth in comparison ...
Simon Ogg, Bashir M. Al-Hashimi
DFT
2009
IEEE
154views VLSI» more  DFT 2009»
14 years 3 months ago
Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...
Qiaoyan Yu, Paul Ampadu
ASIAMS
2007
IEEE
14 years 3 months ago
XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks
Simulation is perhaps the most cost-effective tool to evaluate the operation of a system under design. A flexible, easy to extend, fully object-oriented, and multilayered simulato...
Abbas Nayebi, Sina Meraji, Arash Shamaei, Hamid Sa...
LISA
2008
13 years 11 months ago
Fast Packet Classification for Snort by Native Compilation of Rules
Signature matching, which includes packet classification and content matching, is the most expensive operation of a signature-based network intrusion detection system (NIDS). In t...
Alok Tongaonkar, Sreenaath Vasudevan, R. Sekar
ICCAD
2003
IEEE
144views Hardware» more  ICCAD 2003»
14 years 5 months ago
A High-level Interconnect Power Model for Design Space Exploration
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
Pallav Gupta, Lin Zhong, Niraj K. Jha