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» New Directions in Debugging Hardware Designs
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JSS
2007
120views more  JSS 2007»
13 years 8 months ago
The design and evaluation of path matching schemes on compressed control flow traces
A control flow trace captures the complete sequence of dynamically executed basic blocks and function calls. It is usually of very large size and therefore commonly stored in com...
Yongjing Lin, Youtao Zhang, Rajiv Gupta
ICCD
2008
IEEE
160views Hardware» more  ICCD 2008»
14 years 5 months ago
Fast arbiters for on-chip network switches
— The need for efficient implementation of simple crossbar schedulers has increased in the recent years due to the advent of on-chip interconnection networks that require low la...
Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Gal...
ASPDAC
2006
ACM
153views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Diagonal routing in high performance microprocessor design
This paper presents a diagonal routing method which is applied to an actual microprocessor prototype chip. While including the layout functions for the conventional Manhattan rout...
Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita,...
APIN
2002
121views more  APIN 2002»
13 years 8 months ago
Applying Learning by Examples for Digital Design Automation
This paper describes a new learning by example mechanism and its application for digital circuit design automation. This mechanism uses finite state machines to represent the infer...
Ben Choi
ICCD
2006
IEEE
86views Hardware» more  ICCD 2006»
14 years 5 months ago
Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction
— New back-end design for manufacturability rules have brought guarantee rules for interconnect matching. These rules indicate a certain capacitance matching guarantee given spac...
Rasit Onur Topaloglu, Andrew B. Kahng