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» New Directions in Debugging Hardware Designs
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ACL2
2006
ACM
14 years 1 months ago
A SAT-based procedure for verifying finite state machines in ACL2
We describe a new procedure for verifying ACL2 properties about finite state machines (FSMs) using satisfiability (SAT) solving. We present an algorithm for converting ACL2 conj...
Warren A. Hunt Jr., Erik Reeber
UIST
2004
ACM
14 years 27 days ago
Visual tracking of bare fingers for interactive surfaces
Visual tracking of bare fingers allows more direct manipulation of digital objects, multiple simultaneous users interacting with their two hands, and permits the interaction on l...
Julien Letessier, François Bérard
DAC
1998
ACM
14 years 8 months ago
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
EUROMICRO
2009
IEEE
14 years 2 months ago
Long-Term Planning of Development Efforts by Roadmapping
—Success in the software product business requires timely release of new products and upgrades with proper quality and the right features. For this, a systematic approach for man...
Jarno Vähäniitty, Casper Lassenius, Kris...
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
14 years 1 months ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...