144 search results - page 20 / 29 » New Non-Volatile Memory Structures for FPGA Architectures |
IJCNN
2008
IEEE
14 years 2 months ago
2008
IEEE
— Machine learning has made great progress during the last decades and is being deployed in a wide range of applications. However, current machine learning techniques are far fro...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
ISCA
2010
IEEE
14 years 23 days ago
2010
IEEE
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
CGF
2010
13 years 7 months ago
2010
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...