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» New Results on Instruction Cache Attacks
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DATE
2007
IEEE
98views Hardware» more  DATE 2007»
14 years 1 months ago
A one-shot configurable-cache tuner for improved energy and performance
We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application....
Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A...
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
13 years 11 months ago
The Block-Based Trace Cache
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
Bryan Black, Bohuslav Rychlik, John Paul Shen
MICRO
1997
IEEE
79views Hardware» more  MICRO 1997»
13 years 11 months ago
On High-Bandwidth Data Cache Design for Multi-Issue Processors
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
Jude A. Rivers, Gary S. Tyson, Edward S. Davidson,...
MICRO
1995
IEEE
108views Hardware» more  MICRO 1995»
13 years 11 months ago
SPAID: software prefetching in pointer- and call-intensive environments
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
Mikko H. Lipasti, William J. Schmidt, Steven R. Ku...
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
14 years 20 days ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...