85 search results - page 12 / 17 » New Techniques for Automated Architectural Reconstruction fr... |
DAC
2008
ACM
13 years 9 months ago
2008
ACM
This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topo...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compil...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This paper describes the first application of the Genevieve test generation methodology. The Genevieve approach uses semi-formal techniques derived from "model-checking"...
HASE
2007
IEEE
14 years 1 months ago
2007
IEEE
Fault Tree Analysis (FTA) is a safety-analysis technique that has been recently extended to accommodate product-line engineering for critical domains. This paper describes a tool-...