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DAC
2004
ACM
14 years 10 months ago
A SAT-based algorithm for reparameterization in symbolic simulation
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
DAC
2004
ACM
14 years 10 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw
DAC
2004
ACM
14 years 10 months ago
An analytical approach for dynamic range estimation
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
Bin Wu, Jianwen Zhu, Farid N. Najm
DAC
2005
ACM
14 years 10 months ago
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...
DAC
2005
ACM
14 years 10 months ago
Word level predicate abstraction and refinement for verifying RTL verilog
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
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