Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...