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HPCA
1999
IEEE
13 years 11 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
TPDS
2010
98views more  TPDS 2010»
13 years 5 months ago
The Synchronization Power of Coalesced Memory Accesses
—Multicore architectures have established themselves as the new generation of computer architectures. As part of the one core to many cores evolution, memory access mechanisms ha...
Phuong Hoai Ha, Philippas Tsigas, Otto J. Anshus
IJCAI
2001
13 years 8 months ago
A Layered Brain Architecture for Synthetic Creatures
This paper describes a new layered brain architecture for simulated autonomous and semi-autonomous creatures that inhabit graphical worlds. The main feature of the brain is its di...
Damian A. Isla, Robert C. Burke, Marc Downie, Bruc...
FPGA
1997
ACM
142views FPGA» more  FPGA 1997»
13 years 11 months ago
Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond
Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here, and larger devices shortly after that. We feel that current a...
Jonathan Rose, Dwight D. Hill
ONDM
2000
13 years 8 months ago
Distributed Router Architecture for Packet-Routed Optical Networks
: A new proposal for an optical packet-routed network based on a distributed router architecture in a WDM network is described. Buffering, scheduling and wavelength assignment func...
Michael Düser, Eugene Kozlovski, Robert I. Ki...