This paper presents a new method for using texture to visualize multidimensional data elements arranged on an underlying threedimensional height field. We hope to use simple textu...
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
Graph-theory-based approaches have been used with great success when analyzing abstract properties of natural and artificial networks. However, these approaches have not factored...
We present a Delaunay refinement algorithm for meshing a piecewise smooth complex in three dimensions. The algorithm protects edges with weighted points to avoid the difficulty po...
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...