In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (ZJDL) surrounding the core may restrict the set of test vectors that can be a...
—A new approach for designing t-UED and BUED code checkers is presented. In particular we consider Borden codes for t = 2k − 1, Bose and Bose-Lin codes. The design technique fo...
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
The benefits of virtualized IT environments, such as compute clouds, have drawn interested enterprises to migrate their applications onto new platforms to gain the advantages of ...
Xiaoning Ding, Hai Huang, Yaoping Ruan, Anees Shai...