621 search results - page 30 / 125 » Next Generation Network Processors |
HPDC
1995
IEEE
14 years 5 days ago
1995
IEEE
In this paper, we study the problem of scheduling parallel loops at compile-time for a heterogeneous network of machines. We consider heterogeneity in three aspects of parallel pr...
ASPDAC
2007
ACM
14 years 19 days ago
2007
ACM
The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, ...
CASES
2004
ACM
14 years 11 days ago
2004
ACM
With the ever-increasing pervasiveness of the Internet and its stringent performance requirements, network system designers have begun utilizing specialized chips to increase the ...
CODES
2006
IEEE
14 years 10 days ago
2006
IEEE
During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently don...
ISCA
2003
IEEE
14 years 1 months ago
2003
IEEE
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...