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FCCM
2005
IEEE
102views VLSI» more  FCCM 2005»
14 years 2 months ago
A Signature Match Processor Architecture for Network Intrusion Detection
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the network infrastructu...
Janardhan Singaraju, Long Bu, John A. Chandy
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
14 years 3 months ago
Retargetable Code Optimization for Predicated Execution
Retargetable C compilers are key components of today’s embedded processor design platforms for quickly obtaining compiler support and performing early processor architecture exp...
Manuel Hohenauer, Felix Engel, Rainer Leupers, Ger...
VLSISP
1998
128views more  VLSISP 1998»
13 years 8 months ago
A Low Power DSP Engine for Wireless Communications
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
Ingrid Verbauwhede, Mihran Touriguian
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
14 years 1 months ago
Control network generator for latency insensitive designs
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
Eliyah Kilada, Kenneth S. Stevens
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
14 years 2 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...