256 search results - page 35 / 52 » Noetherian Spaces in Verification |
ICSE
2003
IEEE-ACM
14 years 8 months ago
2003
IEEE-ACM
We show how the state space exploration tool VeriSoft can be used to analyze parallel C/C++ programs compositionally. VeriSoft is used to check assume/guarantee specifications of ...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Simulation of transaction level models (TLMs) is an established embedded systems design technique. Its use cases include virtual prototyping for early software development, platfo...
ICCAD
1997
IEEE
14 years 20 days ago
1997
IEEE
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...
ASPDAC
2007
ACM
14 years 14 days ago
2007
ACM
In today's designs, when functional verification fails, engineers perform debugging using the provided error traces. Reducing the length of error traces can help the debugging...
CAV
2006
Springer
14 years 6 days ago
2006
Springer
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification. In spite of the rich theory developed for system synthesis, litt...