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» Noise considerations in circuit optimization
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ITC
2002
IEEE
114views Hardware» more  ITC 2002»
14 years 20 days ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ASPDAC
2005
ACM
106views Hardware» more  ASPDAC 2005»
13 years 9 months ago
On structure and suboptimality in placement
Abstract— Regular structures are present in many types of circuits. If this structure can be identified and utilized, performance can be improved dramatically. In this paper, we...
Satoshi Ono, Patrick H. Madden
FTEDA
2008
75views more  FTEDA 2008»
13 years 7 months ago
Thermally Aware Design
With greater integration, the power dissipation in integrated circuits has begun to outpace the ability of today's heat sinks to limit the on-chip temperature. As a result, t...
Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
DSD
2010
IEEE
137views Hardware» more  DSD 2010»
13 years 5 months ago
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...
CVPR
2007
IEEE
14 years 9 months ago
A Multi-Scale Tikhonov Regularization Scheme for Implicit Surface Modelling
Kernel machines have recently been considered as a promising solution for implicit surface modelling. A key challenge of machine learning solutions is how to fit implicit shape mo...
Jianke Zhu, Steven C. H. Hoi, Michael R. Lyu