339 search results - page 10 / 68 » Noise-tolerant dynamic circuit design |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
ISCAS
2005
IEEE
14 years 28 days ago
2005
IEEE
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
ISQED
2003
IEEE
14 years 19 days ago
2003
IEEE
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme fo...
VTS
2003
IEEE
14 years 18 days ago
2003
IEEE
We present a novel analog checker that adjusts dynamically the error threshold to the magnitude of its input signals. We demonstrate that this property is crucial for accurate con...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...