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» Noise-tolerant dynamic circuit design
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DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 4 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
ICCAD
1997
IEEE
95views Hardware» more  ICCAD 1997»
14 years 2 months ago
An exact solution to simultaneous technology mapping and linear placement problem
In this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of mini...
Jinan Lou, Amir H. Salek, Massoud Pedram
HPN
1994
13 years 11 months ago
Fast Connection Establishment in the DTM Gigabit Network
Dynamic synchronous Transfer Mode (DTM) is a new protocol suite based on synchronous fast circuit switching. The DTM network is based on bandwidth reservation and supports dynamic...
Per Lindgren, Christer Bohm
ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
14 years 6 months ago
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
ASPDAC
2006
ACM
115views Hardware» more  ASPDAC 2006»
14 years 3 months ago
DraXRouter: global routing in X-Architecture with dynamic resource assignment
In recent years, the X-Architecture is introduced to obtain better performance for integrated circuit physical design. This paper reformulates the global routing problem in X-Archi...
Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hon...