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» Noise-tolerant dynamic circuit design
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PACS
2000
Springer
132views Hardware» more  PACS 2000»
14 years 1 months ago
An Adaptive Issue Queue for Reduced Power at High Performance
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
Alper Buyuktosunoglu, Stanley Schuster, David Broo...
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
14 years 1 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
14 years 4 months ago
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
Anshuman Chandra, Felix Ng, Rohit Kapur
MVA
1996
13 years 11 months ago
Video Enhancement Sensor Using Motion Adaptive Storage Time
We propose a video enhancement sensor for smoothing random noise and getting wide dynamic range. The sensor has computational elements based on a column-parallel architecture. It ...
Takayuki Hamamoto, Kiyoharu Aizawa, Mitsutoshi Hat...
DAC
2007
ACM
14 years 10 months ago
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
Behnam Amelifard, Massoud Pedram