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» Noise-tolerant dynamic circuit design
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DAC
2000
ACM
14 years 10 months ago
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
Hisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima...
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 10 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
ICCD
2006
IEEE
127views Hardware» more  ICCD 2006»
14 years 6 months ago
Power Droop Testing
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power d...
Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd...
BIOSYSTEMS
2007
111views more  BIOSYSTEMS 2007»
13 years 10 months ago
Metastability, criticality and phase transitions in brain and its models
This essay is designed to organize a range of experimental findings and theoretical insights of the past 25 years into a coherent view of the brain’s style of function. The view...
Gerhard Werner
ISQED
2006
IEEE
136views Hardware» more  ISQED 2006»
14 years 3 months ago
An Improved AMG-based Method for Fast Power Grid Analysis
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which need to be modeled accurately in circuit design and verification. Meanwhi...
Cheng Zhuo, Jiang Hu, Kangsheng Chen