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ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
14 years 3 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
IPSN
2005
Springer
14 years 3 months ago
A compact modular wireless sensor platform
— We have designed and constructed a modular platform for use in compact wireless sensing. This platform is based around a series of circuit boards (or panes), each of which inst...
Ari Y. Benbasat, Joseph A. Paradiso
PADS
2003
ACM
14 years 3 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
14 years 4 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
INFOCOM
2010
IEEE
13 years 8 months ago
Analyzing Nonblocking Switching Networks using Linear Programming (Duality)
Abstract—The main task in analyzing a switching network design (including circuit-, multirate-, and photonic-switching) is to determine the minimum number of some switching compo...
Hung Q. Ngo, Atri Rudra, Anh N. Le, Thanh-Nhan Ngu...