Sciweavers

339 search results - page 57 / 68
» Noise-tolerant dynamic circuit design
Sort
View
JCO
2011
115views more  JCO 2011»
13 years 2 months ago
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
Chen Liao, Shiyan Hu
TVLSI
2010
13 years 2 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 19 days ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
14 years 1 months ago
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization
With technology advances, the number of cores integrated on a chip and their speed of operation is increasing. This, in turn is leading to a significant increase in chip temperat...
Srinivasan Murali, Almir Mutapcic, David Atienza, ...
CEC
2007
IEEE
14 years 1 months ago
Evolving neuromodulatory topologies for reinforcement learning-like problems
— Environments with varying reward contingencies constitute a challenge to many living creatures. In such conditions, animals capable of adaptation and learning derive an advanta...
Andrea Soltoggio, Peter Dürr, Claudio Mattius...