325 search results - page 17 / 65 » Non-uniform Instruction Scheduling |
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...
HPCN
1998
Springer
13 years 11 months ago
1998
Springer
This paper presents a new architecture organisation, the dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code of current RISC o...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
HPCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Researchers have searched for scalable alternatives to the symmetric multiprocessor (SMP) architecture since it was first introduced in 1982. This paper introduces an alternative ...
MICRO
1992
IEEE
13 years 11 months ago
1992
IEEE
An important design decision in the implementation of a superscalar processor is the amount of hardware to allocate to the instruction scheduling mechanism. Dynamic scheduling pro...