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» Nonuniform Banking for Reducing Memory Energy Consumption
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TVLSI
2010
13 years 3 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
HIPEAC
2009
Springer
13 years 11 months ago
Accomodating Diversity in CMPs with Heterogeneous Frequencies
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee
ASPLOS
2011
ACM
13 years 5 days ago
Pocket cloudlets
Cloud services accessed through mobile devices suffer from high network access latencies and are constrained by energy budgets dictated by the devices’ batteries. Radio and batt...
Emmanouil Koukoumidis, Dimitrios Lymberopoulos, Ka...
ASPLOS
2012
ACM
12 years 4 months ago
Reflex: using low-power processors in smartphones without knowing them
To accomplish frequent, simple tasks with high efficiency, it is necessary to leverage low-power, microcontroller-like processors that are increasingly available on mobile systems...
Felix Xiaozhu Lin, Zhen Wang, Robert LiKamWa, Lin ...
MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
14 years 1 months ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...