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» Note on alternating directed cycles
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TASE
2011
IEEE
13 years 2 months ago
Multiclass Flow Line Models of Semiconductor Manufacturing Equipment for Fab-Level Simulation
—For multiclass flow line models, we identify a class of service times that allow a decomposition of the system into subsets of servers called channels. In each channel, the cus...
James R. Morrison
ICS
1999
Tsinghua U.
13 years 11 months ago
An experimental evaluation of tiling and shackling for memory hierarchy management
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...
Induprakas Kodukula, Keshav Pingali, Robert Cox, D...
TVLSI
2008
139views more  TVLSI 2008»
13 years 7 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood
MAM
2007
157views more  MAM 2007»
13 years 7 months ago
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
Darrin M. Hanna, Michael DuChene
EUROPKI
2009
Springer
13 years 5 months ago
Automatic Generation of Sigma-Protocols
Efficient zero-knowledge proofs of knowledge (ZK-PoK) are basic building blocks of many cryptographic applications such as identification schemes, group signatures, and secure mult...
Endre Bangerter, Thomas Briner, Wilko Henecka, Ste...