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» Novel CNTFET-based Reconfigurable Logic Gate Design
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ICCD
2005
IEEE
120views Hardware» more  ICCD 2005»
14 years 5 months ago
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...
Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhu...
FPL
2007
Springer
111views Hardware» more  FPL 2007»
14 years 2 months ago
Adaptive Thermoregulation for Applications on Reconfigurable Devices
A biological organism’s ability to sense and adapt to its environment is essential to its survival. Likewise, environmentally aware computing systems avail themselves to a longe...
Phillip H. Jones, James Moscola, Young H. Cho, Joh...
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 2 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
GECCO
2006
Springer
143views Optimization» more  GECCO 2006»
14 years 2 days ago
A hybridized genetic parallel programming based logic circuit synthesizer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung
DATE
2008
IEEE
115views Hardware» more  DATE 2008»
14 years 2 months ago
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi