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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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TVLSI
2008
140views more  TVLSI 2008»
13 years 9 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
JOT
2010
130views more  JOT 2010»
13 years 7 months ago
Test Case Generation Based on State and Activity Models
Abstract We propose a novel testing technique for object-oriented programs. Based on the state and activity models of a system, we construct an intermediate representation, which w...
Santosh Kumar Swain, Durga Prasad Mohapatra, Rajib...
PTS
2010
175views Hardware» more  PTS 2010»
13 years 7 months ago
Test Data Generation for Programs with Quantified First-Order Logic Specifications
We present a novel algorithm for test data generation that is based on techniques used in formal software verification. Prominent examples of such formal techniques are symbolic ex...
Christoph Gladisch
DATE
2000
IEEE
139views Hardware» more  DATE 2000»
14 years 1 months ago
A VHDL Error Simulator for Functional Test Generation
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
Alessandro Fin, Franco Fummi
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
14 years 1 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy