980 search results - page 37 / 196 » Novel Test Pattern Generators for Pseudo-Exhaustive Testing |
ITC
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
ICST
2009
IEEE
14 years 3 months ago
2009
IEEE
The problem of testing from an extended finite state machine (EFSM) can be expressed in terms of finding suitable paths through the EFSM and then deriving test data to follow the ...
ICCD
2006
IEEE
14 years 6 months ago
2006
IEEE
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
CONSTRAINTS
2007
13 years 9 months ago
2007
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...
VTS
2002
IEEE
14 years 2 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...