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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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ITC
2000
IEEE
84views Hardware» more  ITC 2000»
14 years 20 days ago
Non-intrusive BIST for systems-on-a-chip
1 The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within ...
Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wund...
ROMAN
2007
IEEE
127views Robotics» more  ROMAN 2007»
14 years 3 months ago
Incremental on-line hierarchical clustering of whole body motion patterns
Abstract— This paper describes a novel algorithm for autonomous and incremental learning of motion pattern primitives by observation of human motion. Human motion patterns are ed...
Dana Kulic, Wataru Takano, Yoshihiko Nakamura
DAC
2005
ACM
13 years 11 months ago
Path delay test compaction with process variation tolerance
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, T...
ICES
2000
Springer
140views Hardware» more  ICES 2000»
14 years 21 days ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
VTS
2008
IEEE
83views Hardware» more  VTS 2008»
14 years 3 months ago
LS-TDF: Low-Switching Transition Delay Fault Pattern Generation
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
Jeremy Lee, Mohammad Tehranipoor