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DAC
2007
ACM
14 years 10 months ago
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...
Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgo...
ICPP
2005
IEEE
14 years 2 months ago
Design and Implementation of a Parallel Performance Data Management Framework
Empirical performance evaluation of parallel systems and applications can generate significant amounts of performance data and analysis results from multiple experiments as perfo...
Kevin A. Huck, Allen D. Malony, Robert Bell, Alan ...
VTC
2007
IEEE
14 years 3 months ago
Performance Evaluation of A Multiuser Detection Based MAC Design for Ad Hoc Networks
Abstract— In general, the performance and radio resource utilization of Ad Hoc networks are limited by half-duplex operation and possible collisions. In this paper, we propose a ...
Jinfang Zhang, Zbigniew Dziong, François Ga...
IEEECIT
2005
IEEE
14 years 2 months ago
iCDMdt: Focused the Model Mapping and Performance Optimization in Embedded System Design
This paper proposes a method of model-driven HW/SW co-design in embedded system design and discusses the key technology of model mapping, automatic generating codes and performanc...
Jing Luan, Xuan Cheng, Junzhong Gu
ISQED
2005
IEEE
64views Hardware» more  ISQED 2005»
14 years 2 months ago
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET
Double-Gate (DG) transistor has emerged as the most promising device for nano-scale circuit design. Independent control of front and back gate in DG devices can be effectively use...
Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaush...