17409 search results - page 3383 / 3482 » Oblio: Design and Performance |
ICCAD
2008
IEEE
14 years 7 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
ICCAD
2007
IEEE
14 years 7 months ago
2007
IEEE
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
- Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. Ho...
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...