76 search results - page 6 / 16 » On Design and Analysis of a Feasible Network-on-Chip (NoC) A... |
DSN
2006
IEEE
14 years 1 months ago
2006
IEEE
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
DAC
2010
ACM
13 years 9 months ago
2010
ACM
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
DATE
2010
IEEE
14 years 23 days ago
2010
IEEE
Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and becom...
TC
2008
13 years 7 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...