322 search results - page 37 / 65 » On Design and Application Mapping of a Network-on-Chip(NoC) ... |
IPPS
2002
IEEE
14 years 17 days ago
2002
IEEE
In this paper we present new approaches to high performance protein database scanning on two novel massively parallel architectures to gain supercomputer power at low cost. The ...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
CASES
2003
ACM
14 years 27 days ago
2003
ACM
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main ...
IJCSA
2008
13 years 7 months ago
2008
It is well known that transactional and analytical systems each require different database architecture. In general, the database structure of transactional systems is optimized f...