Sciweavers

322 search results - page 54 / 65
» On Design and Application Mapping of a Network-on-Chip(NoC) ...
Sort
View
CVPR
1998
IEEE
14 years 9 months ago
Real-Time 2-D Feature Detection on a Reconfigurable Computer
We have designed and implemented a system for real-time detection of 2-D features on a reconfigurable computer based on Field Programmable Gate Arrays (FPGA `s). We envision this ...
Arrigo Benedetti, Pietro Perona
DAC
2003
ACM
14 years 8 months ago
Data communication estimation and reduction for reconfigurable systems
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
Adam Kaplan, Philip Brisk, Ryan Kastner
HPCA
2006
IEEE
14 years 8 months ago
The common case transactional behavior of multithreaded programs
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen...
CHI
2003
ACM
14 years 8 months ago
iStuff: a physical user interface toolkit for ubiquitous computing environments
The iStuff toolkit of physical devices, and the flexible software infrastructure to support it, were designed to simplify the exploration of novel interaction techniques in the po...
Rafael Ballagas, Meredith Ringel, Maureen C. Stone...
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
14 years 4 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras