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» On Designing Software Architectures
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139
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ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
15 years 9 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
15 years 9 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
15 years 9 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
137
Voted
MICRO
2006
IEEE
98views Hardware» more  MICRO 2006»
15 years 9 months ago
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
Chrysostomos Nicopoulos, Dongkook Park, Jongman Ki...
160
Voted
ACMICEC
2006
ACM
142views ECommerce» more  ACMICEC 2006»
15 years 9 months ago
Trusting advice from other buyers in e-marketplaces: the problem of unfair ratings
In electronic marketplaces populated by self-interested agents, buyer agents would benefit by modeling the reputation of seller agents, in order to make effective decisions abou...
Jie Zhang, Robin Cohen
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