87 search results - page 3 / 18 » On Discretization of Delays in Timed Automata and Digital Ci... |
ICCAD
2003
IEEE
14 years 7 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
JCO
2011
13 years 5 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
—The advanced sampling and variance reduction techniques as efficient alternatives to the slow crude-MC method have recently been adopted for the analysis of timing yield in dig...
ICCAD
1999
IEEE
14 years 3 months ago
1999
IEEE
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...
CORR
2010
Springer
13 years 11 months ago
2010
Springer
This paper illustrates a technique for specifying the detailed timing, logical operation, and compositional circuit design of digital circuits in terms of ordinary state machines w...