372 search results - page 51 / 75 » On Fault Testing for Reversible Circuits |
135
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ICCD
2003
IEEE
16 years 17 days ago
2003
IEEE
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
134
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VTS
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
127
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EVOW
2006
Springer
15 years 7 months ago
2006
Springer
Abstract. We motivate and describe an analog evolvable hardware design platform named GRACE (i.e. Generative Robust Analog Circuit Exploration). GRACE combines coarse-grained, topo...
135
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VLSID
2001
IEEE
16 years 4 months ago
2001
IEEE
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...
132
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TVLSI
2008
15 years 3 months ago
2008
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...