216 search results - page 18 / 44 » On High-Bandwidth Data Cache Design for Multi-Issue Processo... |
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...