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CORR
2010
Springer
58views Education» more  CORR 2010»
13 years 6 months ago
Realizable Paths and the NL vs L Problem
A celebrated theorem of Savitch [Sav70] states that NSPACE(S) ⊆ DSPACE(S2 ). In particular, Savitch gave a deterministic algorithm to solve ST-CONNECTIVITY (an NL-complete probl...
Shiva Kintali
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
12 years 11 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
12 years 10 months ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
ICC
2009
IEEE
14 years 2 months ago
Separable Implementation of L2-Orthogonal STC CPM with Fast Decoding
In this paper we present an alternative separable implementation of L2 -orthogonal space-time codes (STC) for continuous phase modulation (CPM). In this approach, we split the STC...
Matthias Hesse, Jérôme Lebrun, Lutz H...
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
14 years 2 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks