A celebrated theorem of Savitch [Sav70] states that NSPACE(S) ⊆ DSPACE(S2 ). In particular, Savitch gave a deterministic algorithm to solve ST-CONNECTIVITY (an NL-complete probl...
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
In this paper we present an alternative separable implementation of L2 -orthogonal space-time codes (STC) for continuous phase modulation (CPM). In this approach, we split the STC...
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...