In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
This paper presents for the first time low energy simultaneous memory and register allocation. A minimum cost network flow approach is used to efficiently solve for minimum energy...
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
This paper describes a technique for calculating the switching activity of a set of registers shared by dierent data values. Based on the assumption that the joint pdf (probabili...
Iterated Register Coalescing (IRC) is a widely used heuristic for performing register allocation via graph coloring. Many implementations in existing compilers follow (more or less...