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WCE
2007
13 years 9 months ago
A Graph-based Framework for High-level Test Synthesis
Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniq...
Ali Pourghaffari bashari, Saadat Pourmozafari
IEEEPACT
2002
IEEE
14 years 1 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
APLAS
2006
ACM
14 years 10 days ago
Combining Offline and Online Optimizations: Register Allocation and Method Inlining
Abstract. Fast dynamic compilers trade code quality for short compilation time in order to balance application performance and startup time. This paper investigates the interplay o...
Hiroshi Yamauchi, Jan Vitek
PLDI
2004
ACM
14 years 2 months ago
Balancing register allocation across threads for a multithreaded network processor
+ Modern network processors employ multi-threading to allow concurrency amongst multiple packet processing tasks. We studied the properties of applications running on the network p...
Xiaotong Zhuang, Santosh Pande
MICRO
2003
IEEE
121views Hardware» more  MICRO 2003»
14 years 1 months ago
Exploiting Value Locality in Physical Register Files
The physical register file is an important component of a dynamically-scheduled processor. Increasing the amount of parallelism places increasing demands on the physical register...
Saisanthosh Balakrishnan, Gurindar S. Sohi