53 search results - page 4 / 11 » On Minimization of Peak Power for Scan Circuit during Test |
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
ISVLSI
2003
IEEE
14 years 22 days ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
CEC
2005
IEEE
14 years 1 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...