1187 search results - page 104 / 238 » On Modeling Cross-Talk Faults |
ISCAS
2007
IEEE
14 years 3 months ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
ICES
2003
Springer
14 years 2 months ago
2003
Springer
In this article, we introduce the approach to the realization of ontogenetic development and fault tolerance that will be implemented in the POEtic tissue, a novel reconfigurable ...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
An incremental simulation-based approach to fault diagnosis and logic debugging is presented. During each iteration of the algorithm, a single suspicious location is identified a...