Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. R...
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisi...
Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lomb...
Intrusion-tolerance is the technique of using fault-tolerance to achieve security properties. Assuming that faults, both benign and Byzantine, are unavoidable, the main goal of Int...
Abstract. The common goals of the Grid and peer-to-peer communities have brought them in close proximity. Both the technologies overlay a collaborative resource-sharing infrastruct...
Kaizar Amin, Gregor von Laszewski, Armin R. Mikler